Chapter 1 figs

Chapter 1 figs

Alan Robert Clark

Feb 7, 2001

Note that the source code for the figs can be seen by clicking the pic. You will need to use your Browser's BACK button to return to this page.

cctgif/Comparator.gif

Figure 1: The Comparator

cctgif/Hysteresis.gif

Figure 2: Positive Feedback causes state-dependant thresholds

cctgif/NOTGate.gif

Figure 3: An Inverter

cctgif/ANDGate.gif

Figure 4: The AND Gate

cctgif/ORGate.gif

Figure 5: The OR Gate

cctgif/NANDGate.gif

Figure 6: The NAND Gate

cctgif/NORGate.gif

Figure 7: The NOR Gate.

cctgif/XORGate.gif

Figure 8: The XOR Gate

cctgif/HalfAdder.gif

Figure 9: A Half Adder

cctgif/FullAdder.gif

Figure 10: A Full Adder

cctgif/3BitAdder.gif

Figure 11: 3 Bit Adder!

cctgif/Decoder.gif

Figure 12: Simplest decoder to select between two 4-byte memories

cctgif/Hazard.gif

Figure 13: Timing Hazard.

cctgif/RSFlipFlop.gif

Figure 14: The RS (Reset-Set) Flip Flop

cctgif/NandRS.gif

Figure 15: A Nand-based RS Flip Flop.

cctgif/RSDebounce.gif

Figure 16: An RS Flip Flop used in debouncing

cctgif/ClockedRS.gif

Figure 17: A Clocked RS Flip Flop

cctgif/DLatch.gif

Figure 18: NAND gate D Latch

cctgif/EdgeDLatch.gif

Figure 19: A neg Edge Triggered Master-Slave Flip Flop

Chapter 3 examples Back to Circuit macros Back to my Home Page




File translated from TEX by TTH, version 2.86.
On 7 Feb 2001, 13:43.